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LTC1235 Microprocessor Supervisory Circuit
FEATURES
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DESCRIPTIO
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Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max.) Onboard Gating of RAM Chip Enable Signals Conditional Battery Backup Extends Battery Life 4.65V Precision Voltage Monitor Power OK/Reset Time Delay: 200ms External Reset Control Minimum External Component Count 1A Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature All the LTC695 Features Plus Conditional Battery Backup and External Reset Control
The LTC1235 provides complete power supply monitoring and battery control functions for microprocessor reset, battery backup, RAM write protection, power failure warning and watchdog timing. The LTC1235 has all the LTC695 features plus conditional battery backup and external reset control. When an out-of-tolerance power supply condition occurs, the reset outputs are forced to active states and the Chip Enable output write-protects external memory. The RESET output is guaranteed to remain logic low with VCC as low as 1V. External reset control is provided by a debounced push-button reset input. The LTC1235 powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, provides backup power to the RAMs. The LTC1235 can be programmed by a P signal to either back up the RAMs or not. This extends the battery life in situations where RAM data need not always be saved when power goes down. For an early warning of impending power failure, the LTC1235 provides an internal comparator with a userdefined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to the time-out period.
APPLICATI
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Critical P Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems
TYPICAL APPLICATI
VIN 7.5V LT1086-5
BATTERY LIFE (NORMALIZED)
+
10F
VIN ADJ
VOUT
+5V
+
100F
VCC 0.1F
VOUT LTC1235 0.1F
POWER TO P CMOS RAM POWER I/O LINE P RESET P NMI I/O LINE P SYSTEM
VBATT 51k +3V PFI PB RST 10k
BACKUP RESET PFO WDI
LTC1235 TA1
THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA. IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE P REQUESTS BACKUP WITH THE BACKUP PIN.
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Battery Life vs Backup Duty Cycle
10 9 8 7 6 5 4 3 2 1 0 0 20 60 80 40 BACKUP DUTY CYCLE (%) 100 LTC695 (WITHOUT CONDITIONAL BATTERY BACKUP) LTC1235
LTC1235 TA02
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LTC1235 ABSOLUTE AXI U RATI GS U WW
RESET RESET WDO CE IN CE OUT WDI PFO PFI
S PACKAGE 16-LEAD PLASTIC SOL
TJMAX = 110C, JA = 130C/W CONDITIONS: PCB MOUNT ON FR4 MATERIAL, STILL AIR AT 25C, COPPER TRACE
Terminal Voltage VCC .................................................... -0.3V to 6.0V VBATT ................................................. -0.3V to 6.0V All Other Inputs .................... -0.3V to (VCC + 0.3V) Input Current VCC .............................................................. 200mA VBATT ............................................................. 50mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VBATT VOUT VCC GND BATT ON LOW LINE PB RST BACKUP 1 2 3 4 5 6 7 8 LTC1235 16 15 14 13 12 11 10 9
ORDER PART NUMBER LTC1235CN
N PACKAGE 16-LEAD PLASTIC DIP
TJMAX = 110C, JA = 130C/W
PRODUCT SELECTIO GUIDE
PINS LTC1235 LTC690 LTC691 LTC694 LTC695 LTC699 LTC1232 16 8 16 8 16 8 8 RESET X X X X X X X WATCHDOG TIMER X X X X X X X BATTERY BACKUP X X X X X POWER FAIL WARNING X X X X X RAM WRITE PROTECT X X X X PUSH-BUTTON RESET X CONDITIONAL BATTERY BACKUP X
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(Notes 1 and 2)
VOUT Output Current .................. Short Circuit Protected Power Dissipation ............................................. 500mW Operating Temperature Range LTC1235C ............................................ 0C to 70C Storage Temperature Range ................ -65C to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
(Note 3)
TOP VIEW VBATT VOUT VCC GND BATT ON LOW LINE PB RST BACKUP 1 2 3 4 LTC1235 5 6 7 8 12 11 10 9 16 PRESET 15 14 13 PRESET WDO CE IN CE OUT WDI PFO PFI
ORDER PART NUMBER LTC1235CS
LTC1235
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25C, unless otherwise noted.
PARAMETER Battery Backup Switching Operating Voltage Range VCC VBATT VOUT Output Voltage IOUT = 1mA
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CONDITONS
MIN
TYP
MAX
UNITS
4.75 2.00 VCC - 0.05 VCC - 0.1 VCC - 0.5 VCC - 0.005 VCC - 0.005 VCC - 0.25
5.50 4.25
V V
IOUT = 50mA BACKUP Input Threshold VCC > Reset Voltage Threshold Logic Low Logic High IOUT = 250A, VCC < VBATT VCC < VBATT 1M Pulldown on VOUT IOUT 50mA
q
0.8 2.0 3 VBATT - 0.1 VBATT - 0.02 0 0.6 0.6 0.04 0.04 -0.1 -1.0 70 50 20 0.4 0.5 35 1 25 0.8 2.0
q
V A V V
BACKUP Pullup Current (Note 4) VOUT in Battery Backup Mode (Note 5) VOUT in Battery Saving Mode (Note 5) VCC Supply Current (excluding IOUT) Battery Supply Current in Battery Backup Mode and Battery Saving Mode (Note 5) Battery Standby Current (+ = Discharge, - = Charge) Battery Switchover Threshold VCC - VBATT Battery Switchover Hysteresis BATT ON Output Voltage (Note 6) BATT ON Output Short Circuit Current (Note 6) Push-Button Reset PB RST Input Threshold PB RST Input Low Time (Notes 4, 7) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time Watchdog Time-out Period Reset Active Time PSRR Watchdog Time-out Period PSRR Minimum WDI Input Pulse Width RESET Output Voltage At VCC = 1V RESET and LOW LINE Output Voltage (Note 6) VIL = 0.4V, VIH = 3.5V ISINK = 10A, VCC = 1V ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1A, VCC = 5V 3.5
q q
1.5 2.5 1 5 +0.02 +0.10
mA A A mV mV V mA A V ms
VCC = 0V, VBATT = 2.8V
q
5.5 > VCC > VBATT + 0.2V
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Power Up Power Down ISINK = 3.2mA BATT ON = VOUT Sink Current BATT ON = 0V Source Current Logic Low Logic High
40 4.5 160 140 1.2 1.0 4.65 40 200 200 1.6 1.6 1 8 200 4 200 0.4 4.75 240 280 2.00 2.25
V mV ms sec ms/V ms/V ns mV V
VCC = 5V
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VCC = 5V
q
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LTC1235
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25C, unless otherwise noted.
PARAMETER RESET and WDO Output Voltage (Note 6) RESET, RESET, WDO, LOW LINE Output Short Circuit Current (Note 6) WDI Input Threshold WDI Input Current Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR PFI Input Current PFO Output Voltage (Note 6) PFO Short Circuit Source Current (Note 6) PFI Comparator Response Time (falling) PFI Comparator Response Time (rising) (Note 6) Chip Enable Gating CE IN Threshold CE IN Pullup Current (Note 4) CE OUT Output Voltage ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1A, VCC = 0V VCC = 5V, CL = 20pF
q
CONDITONS ISINK = 1.6mA, VCC = 5V SOURCE = 1A, VCC = 4.25V Output Source Current Output Sink Current Logic Low Logic High WDI = VOUT WDI = 0V VCC = 5V
q q
MIN 3.5 1
TYP
MAX 0.4
UNITS V A mA V A
3 25
25 0.8
2.0 -50 1.25 4 -8 1.3 0.3 0.01 25 0.4 3.5 1 3 30 2 40 8 0.8 2.0 3 0.4 VOUT - 1.50 VOUT - 0.05 20 20 30 35 35 45 ns mA A V 25 A mA s s 50
q
1.35
V mV/V nA V
ISINK = 3.2mA ISOURCE = 1A PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT VIN = -20mV, VOD = 15mV VIN = 20mV, VOD = 15mV with 10k Pullup VIL VIH
V
CE Propagation Delay CE OUT Output Short Circuit Current
Output Source Current Output Sink Current
The q denotes specifications which apply over the operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts, consult the factory. Note 4: The input pins of PB RST, BACKUP and CE IN, have weak internal pullups which pull to the supply when the input pins are floating. Note 5: The LTC1235 can be programmed either to provide or not to provide battery backup power to the VOUT pin during power failure. The power down condition of VOUT is selected by the logic level of the BACKUP pin which is latched internally when VCC falls through the reset voltage threshold. If the latched logic level of the BACKUP pin is high, VOUT will be
in Battery Backup Mode and will be switched to VBATT when VCC falls below VBATT. If the latched logic level of the BACKUP pin is low, VOUT will be in Battery Saving Mode when VCC falls below VBATT. Note 6: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pullups of typically 3A. However, external pullup resistors may be used when higher speed is required. Note 7: The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset outputs go to the active states. The reset outputs will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level.
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LTC1235
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT vs IOUT
5.00 VCC = 5V VBATT = 2.8V TA = 25C 2.80 VCC = 0V VBATT = 2.8V TA = 25C BACKUP MODE SELECTED
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.78 SLOPE = 125 2.76
PFI INPUT THRESHOLD (V)
4.95 4.90 SLOPE = 5 4.85
4.80
4.75
0
10
30 40 20 LOAD CURRENT (mA)
RESET Output Voltage vs Supply Voltage
5 TA = 25C EXTERNAL PULLUP = 10A VBATT = 0V 232
RESET VOLTAGE THRESHOLD (V)
RESET OUTPUT VOLTAGE (V)
RESET ACTIVE TIME (ms)
4 3
2
1
0
0
1
3 4 2 SUPPLY VOLTAGE (V)
Power Fail Comparator Response Time
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
6 5 4 3 2 1 0
VPFI 1.3V + - PFO 30pF
VCC = 5V TA = 25C
1.305V 1.285V 0 1
VPFI = 20mV STEP
2
345 TIME (s)
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UW
50
LTC1235 G01
VOUT vs IOUT
1.308 1.306 1.304 1.302 1.300 1.298 1.296 2.72
Power Failure Input Threshold vs Temperature
VCC = 5V
2.74
0
100
300 400 200 LOAD CURRENT (A)
500
1.294 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
LTC1235 G02
LTC1235 G03
Reset Active Time vs Temperature
4.66 VCC = 5V 224 216 208 200 192 184 -50 -25 4.65 4.64 4.63 4.62 4.61
Reset Voltage Threshold vs Temperature
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LTC1235 G04
50 25 75 0 TEMPERATURE (C)
100
125
4.60 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
LTC1235 G05
LTC1235 G06
Power Fail Comparator Response Time
6 5 4 3 2 1 0
VPFI 1.3V + - PFO 30pF
Power Fail Comparator Response Time with Pullup Resistor
6 5 4 3 2 1 0
+5V VPFI 1.3V + - PFO 10k 30pF
VCC = 5V TA = 25C
VCC = 5V TA = 25C
1.315V 1.295V 7 8 0
VPFI = 20mV STEP
1.315V 1.295V 0 2
VPFI = 20mV STEP
20 40
60 80 100 120 140 160 180 TIME (s)
LTC1235 G08
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6
8 10 12 14 16 18 TIME (s)
LTC1235 G09
LTC1235 G07
5
LTC1235
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VCC: +5V supply input. The VCC pin should be bypassed with a 0.1F capacitor. Backup: Logic input to control the PMOS switch, M2, when VCC is lower than VBATT. While VCC is falling through the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is latched in Memory Logic and used to turn on or off M2 when VCC is below VBATT. If the latched status of the BACKUP pin is high, the Memory Logic turns on M2 when VCC falls to 50mV greater than VBATT. If the latched status of the BACKUP pin is low, the Memory Logic keeps M2 off even after VCC falls below VBATT. If the BACKUP pin is left floating it will be pulled high by an internal pullup and the LTC1235 will provide battery backup when VCC falls. VOUT: Voltage output for backed up memory. Bypass with a capacitor of 0.1F or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical on resistance of 5. When VCC is lower than VBATT, the status of the BACKUP pin stored in Memory Logic controls M2. If the status is high, the Memory Logic turns on M2 and VOUT is internally switched to VBATT through M2. If the status is low, the Memory Logic keeps M2 off and VOUT is in Battery Saving Mode. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Backup battery input. When VCC falls below VBATT, the status of the BACKUP pin stored in the Memory Logic controls M2. If the status is high, auxiliary power, connected to VBATT is delivered to VOUT through M2. If the status is low, the Memory Logic keeps M2 off and VOUT is in Battery Saving Mode. If backup battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground pin. BATT ON: Battery on logic output from comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VCC falls below VBATT, if the status of the BACKUP pin stored in Memory Logic is high and VOUT is switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. PB RST: Logic input for direct connection to a pushbutton. The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces RESET to active low. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level. RESET: Logic output for P reset control. The LTC1235 provides three ways to generate P reset. First, whenever VCC falls below either the reset voltage threshold (4.65V, typically) or VBATT, RESET goes active low. After VCC returns to 5V, the reset pulse generator forces RESET to remain active low for a minimum of 140ms. Second, when the watchdog timer is enabled but not serviced prior to the time-out period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for every time-out period (see Figure 11). Third, when the PB RST pin stays active low for a minimum of 40ms, RESET is forced low by reset pulse generator. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level. RESET: RESET is an active high logic output. It is the inverse of RESET. LOW LINE: Logic output from comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.65V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1).
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LTC1235
PI FU CTIO S
WDI: Watchdog Input, WDI, is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11). WDO: Watchdog logic output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic input to the Chip Enable gating circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 6 for additional information. CE OUT: Logic output from the Chip Enable gating circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 6).
BLOCK DIAGRA
VBATT VCC BACKUP
CE IN - PFO PFI OSC RESET RESET PULSE GENERATOR RESET +
PB RST
WDI
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M2 M1 MEMORY LOGIC CHARGE PUMP - C2 +
VOUT
BATT ON
LOW LINE + C1 - 1.3V
CE OUT
GND
LEVEL SENSE AND DEBOUNCE
TRANSITION DETECTOR
WATCHDOG TIMER
WDO
LTC1235 BD
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LTC1235
APPLICATI S I FOR ATIO U
To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1F capacitor with the leads trimmed as short as possible. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold. Push-Button Reset The LTC1235 provides an logic input pin for direct connection to a push-button. The push-button reset input, PB RST, requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces the reset outputs to active states. The reset signals will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level (Figure 2).
V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 V1 t1 t1 = RESET ACTIVE TIME
LTC1235 F01
Power Monitoring The LTC1235 uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When VCC falls below the reset voltage threshold, the reset outputs are forced to active states. The reset voltage threshold accounts for a 5% variation on VCC, so the reset outputs become active when VCC falls below 4.75V (4.65V typical). On power-up, the reset signals are held active states for a minimum of 140ms after the reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the reset outputs. Response time is typically 10s.
V2 VCC
RESET
t1
LOW LINE
VCC = 5V PB RST t1 LOGIC LOW LOGIC HIGH t2 RESET RESET t1 = PUSH-BUTTON RESET LOW TIME t2 = RESET ACTIVE TIME LOGIC HIGH LOGIC LOW
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Figure 1. Reset Active Time
Figure 2. Push-Button Reset
LTC1235
APPLICATI
S I FOR ATIO
Voltage Output During normal operation, the LTC1235 uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5. The VOUT pin should be bypassed with a capacitor of 0.1F or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC - VOUT voltage differential) is desired, the LTC1235 provides BATT ON output to drive the base of external PNP transistor (Figure 3). Another alternative to provide higher current is to connect a high current Schottky diode from the VCC pin to the VOUT pin to supply the extra current.
ANY PNP POWER TRANSISTOR
R1 BATT ON VOUT VCC LTC1235 VBATT GND
LTC1235 F03
+5V 0.1F
0.1F
+3V
Figure 3. Using BATT ON to Drive External PNP Transistor
The LTC1235 is protected for safe area operation with short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. The threshold temperature for thermal shutdown is approximately 155C with about 10C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. LTC1235
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uses a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by VBATT pin is strictly junction leakage. Conditional Battery Backup LTC1235 provides an unique feature to either allow VOUT to be switched to VBATT or to disable the CMOS RAM battery backup function when primary power is lost. Disabling the battery backup function is useful in conserving the backup battery's life when the SRAM doesn't need battery backup during long term storage of a computer system, or delivery of the computer system to the end user. The BACKUP pin (Pin 8) is used to serve this feature on power-down. When VCC is falling through the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is stored in the Memory Logic (see BLOCK DIAGRAM). If the stored status is logic high and VCC fall to 50mV greater than VBATT, a 125 PMOS switch, M2, connects the VBATT input to VOUT and the battery switchover comparator, C2, shuts off the NMOS power switch, M1. M2 is designed for very low dropout voltage (input-tooutput differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. If the stored status is logic low and VCC falls to 50mV greater than VBATT, the Memory Logic keeps M2 off and C2 shuts off M1. VOUT is in Battery Saving Mode (see Figure 4). The supply current in both mode is 1A maximum. On power-ups, C2 keeps M1 off before VCC reaches 70mV higher than VBATT. On the first power-up after the battery is replaced (with power off), the status stored in the Memory Logic is undetermined. VOUT could be either in Battery Backup Mode or in Battery Saving Mode. When VCC is 70mV greater than VBATT, M1 connects VOUT to VCC. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT and the status stored in the Memory Logic is high. The response time of C2 is approximately 20s.
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LTC1235
APPLICATI
BACKUP
S I FOR ATIO
VOUT IN BATTERY SAVING MODE
LOGIC LOW
VCC
RESET VOLTAGE THRESHOLD VBATT
VOUT
Hi-Z
VOUT IN BATTERY BACKUP MODE BACKUP LOGIC HIGH
VCC
RESET VOLTAGE THRESHOLD VBATT
VOUT
VOUT = VBATT
LTC1235 F04
Figure 4. Conditional Battery Backup Operation
The operating voltage at the VBATT pin ranges from 2.0V to 4.25V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term memory backup instead of a battery. For capacitor backup, see Typical Applications. The charging resistor for recharging rechargeable batteries should be connected to VOUT through a diode since this eliminates the discharge path that exists when VCC collapses and RAM is not backed up (Figure 5).
V - VBATT - VD I = OUT R R +5V 0.1F LTC1235 BACKUP VBATT GND 4 I/O LINE P
LTC1235 F05
1N4148
VCC
VOUT 0.1F RAM
+3V
Figure 5. Charging External Battery Through VOUT
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Replacing the Backup Battery with Power On When changing the backup battery with system power on, spurious resets can occur while battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC1235 switches to battery backup or battery saving mode. In either case, the battery supply current pulls VBATT low and the device goes back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, two methods can be used to eliminate this problem. First, a capacitor from VBATT to GND will allow time for battery replacement by slowing the charge rate. For example, the battery standby current is 1A maximum over temperature and the external capacitor required to slow the charge rate is: 1A CEXT TREQ'D VCC - VBATT where TREQ'D is the maximum time required to replace the backup battery. With VCC = 4.5V, VBATT = 3V and TREQ'D = 3 sec, the value for external capacitor is 2F. Second, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1A maximum over temperature and the external resistor required to hold VBATT below VCC is:
V - 50mV R CC 1A With VCC = 4.5V, a 4.3M resistor will work. With a 3V battery, this resistor will draw only 0.7A from the battery, which is negligible in most cases.
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If the battery connections are made with long wires or PC traces, inductive spikes can be generated during battery replacement. Even if a resistor is used to prevent spurious resets as described above, these spikes can take the VBATT pin below GND violating the LTC1235 absolute maximum ratings. A 0.1F capacitor from VBATT to GND is recommended to eliminate these potential spikes when battery replacement is made through long wires.
LTC1235
APPLICATI
S I FOR ATIO
Table 1 shows the state of each pin during battery backup. If the backup battery is not used, connect VBATT to GND and VOUT to VCC.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL VCC BACKUP VOUT VBATT BATT ON PFI PFO PB RST RESET RESET WDI WDO CE IN CE OUT STATUS C2 monitors VCC for active switchover. BACKUP is ignored. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1A maximum. Logic high. The open circuit output voltage is equal to VOUT. Power Failure Input is ignored. Logic low PB RST is ignored. Logic low Logic high. The open circuit output voltage is equal to VOUT. Watchdog Input is ignored. Logic high. The open circuit output voltage is equal to VOUT. Chip Enable Input is ignored. Logic high. The open circuit output voltage is equal to VOUT.
LOW LINE Logic low
Memory Protection The LTC1235 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two pins, CE
BACKUP = VCC VCC V2 V1
CE IN
CE OUT VOUT = VBATT
Figure 6. Timing Diagram for CE IN and CE OUT
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IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is +5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 6 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor's address decoder output. Figure 7 shows a typical nonvolatile CMOS RAM application.
+5V 0.1F VCC VOUT
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VCC 10F 0.1F 62512 RAM CS 20ns PROPAGATION DELAY FROM DECODER GND
LTC1235 CE OUT VBATT +3V GND CE IN BACKUP RESET
TO P
LTC1235 F06
Figure 7. A Typical Nonvolatile CMOS RAM Application
V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS
VOUT = VBATT
LTC1235 F06
11
LTC1235
APPLICATI
S I FOR ATIO
Power Fail Warning The LTC1235 generates a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at PFI pin falls below 1.3V several milliseconds before the +5V supply falls below the maximum reset voltage threshold 4.75V. PFO is normally used to interrupt the microprocessor to execute shut-down procedure between PFO and RESET or RESET. The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin. R1 R1 VH = 1.3V 1+ + R2 R3 When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction. R1 (5V - 1.3V)R1 VL = 1.3V 1 + - R2 1.3V(R3 + R4)
Assuming R4R3,VHYSTERESIS = 5V R1 R3
Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shut-down procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.5V which 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.75V + 1.5V) and VHYSTERESIS = 850mV.
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VHYSTERESIS = 5V R1 = 850mV R3
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R3 5.88 R1 Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3. 51k (5V - 1.3V)51k 7.5V = 1.3V 1+ - R2 1.3V(310k) R2 = 9.7k, Choose nearest 5% resistor 10k and recalculate VL, 51k (5V - 1.3V)51k VL = 1.3V 1 + - = 7.32V 1.3V(310k) 10k 51k 51k VH = 1.3V 1 + + = 8.151V 10k 300k
(7.32V - 6.25V) = 10.7ms 100mV/ms
VHYSTERESIS = 8.151V - 7.32V = 831mV
VIN 7.5V 10F R1 51k LT1086-5 VIN VOUT ADJ +5V
+
+
VCC LTC1235 PFO BACKUP PFI GND TO P
100F R3 300k
0.1F R4 10k
R2 10k
LTC1235 F07
Figure 8. Monitoring Unregulated DC Supply with the LTC1235 Power Fail Comparator
VIN 6.5V LT1086-5 VIN VOUT ADJ 10F 0.1F VCC LTC1235 PFO BACKUP PFI GND
+5V R1 27k R4 10k R3 2.7M
+
10F
+
TO P
R2 8.2k R5 3.3k
LTC1235 F08
Figure 9. Monitoring Regulated DC Supply with the LTC1235 Power Fail Comparator
LTC1235
APPLICATI
S I FOR ATIO
The 10.7ms allows enough time to execute shut-down procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN. Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure that the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.85V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. Watchdog Timer The LTC1235 provides a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within the time-out period, the reset outputs are forced to active states for a minimum of 140ms. The watchdog time-out period is fixed at 1.0 second minimum on the LTC1235. This time-out period provides adequate time for many systems to service the watchdog timer immediately after a reset. Figure 11 shows the timing diagram of
VCC = 5V WDI
WDO
t2
RESET
t1
Figure 11. Watchdog Time-out Period and Reset Active Time
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watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as the reset outputs are inactive. When either a high-to-low or low-tohigh transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT. The Watchdog Output, WDO, goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT.
+5V VBATT R1 1M PFI +3V R2 1M CE OUT BACKUP CE IN GND VCC PFO LTC1235 LOW BATTERY SIGNAL TO P I/O PIN
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TO P I/O PIN
RL 20K OPTIONAL TEST LOAD
LTC1235 F09
Figure 10. Backup Battery Monitor with Optional Test Load
t1 = RESET ACTIVE TIME t2 = WATCHDOG TIME-OUT PERIOD
t2
t1
t1
LTC1235 F11
13
LTC1235
TYPICAL APPLICATI
Capacitor Backup with 74HC4016 Switch
+5V VCC 0.1F R1 10k 1 R2 30k 10 11 12 14 74HC4016 7 13 100F 2 LTC1235 VBATT LOW LINE VOUT 0.1F
+
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Write Protect for Additional RAMs
0.1F +5V 0.1F VCC LTC1235 CE OUT VBATT +3V BACKUP CE IN LOW LINE GND
GND
VOUT
+
10F
VCC 62512 RAMA CS
20ns PROPAGATION DELAY
0.1F VCC 62128 RAMB CS1 CS2 CSC 0.1F VCC 62128 RAMC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs
LTC1235 TA4
CSA
LTC1235 TA3
CSB
P SYSTEM
LTC1235
PACKAGE DESCRIPTIO
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381) +0.025 0.325 -0.015
0.015 (0.381) MIN
(8.255 +0.635) -0.381
0.005 (0.127) RAD MIN
0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143)
0.009 - 0.013 (0.229 - 0.330)
SEE NOTE 0.016 - 0.050 (0.406 - 1.270)
NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead Plastic DIP
0.770 (19.558) 16 15 14 13 12 11 10 9
0.260 0.010 (6.604 0.254)
1 0.130 0.005 (3.302 0.127)
2
3
4
5
6
7
8
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP
0.125 (3.175) MIN
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
0.018 0.003 (0.457 0.076)
N16 1291
SO Package 16-Lead SOIC
0.398 - 0.413 (10.109 - 10.490) 16 15 14 13 12 11 10 9
SEE NOTE
0.394 - 0.419 (10.008 - 10.643)
1
2
3
4
5
6
7
8
0 - 8 TYP
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305)
0.014 - 0.019 (0.356 - 0.483) TYP
SOL16 12/91
15
LTC1235
U.S. Area Sales Offices
NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E. Lincoln Hwy.,Suite 306 Langhorne, PA 19047 Phone: (215) 757-8578 FAX: (215) 757-5631 SOUTHEAST REGION Linear Technology Corporation 17060 Dallas Parkway Suite 208 Dallas, TX 75248 Phone: (214) 733-3071 FAX: (214) 380-5138 CENTRAL REGION Linear Technology Corporation Chesapeake Square 229 Mitchell Court, Suite A-25 Addison, IL 60101 Phone: (708) 620-6910 FAX: (708) 620-6977 SOUTHWEST REGION Linear Technology Corporation 22141 Ventura Blvd. Suite 206 Woodland Hills, CA 91364 Phone: (818) 703-0835 FAX: (818) 703-0517 NORTHWEST REGION Linear Technology Corporation 782 Sycamore Dr. Milpitas, CA 95035 Phone: (408) 244-2050 FAX: (408) 432-6331
International Sales Offices
FRANCE Linear Technology S.A.R.L. "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Mallabry France Phone: 33-1-46316161 (170) FAX: 33-1-46314613 KOREA Linear Technology Korea Branch Namsong Building, #505 Itaewon-Dong 260-199 Yongsan-Ku, Seoul Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 011-44-276-677676 FAX: 011-44-276-64851
JAPAN Linear Technology KK 4F Ichihashi Building 1-8-4 Kudankita Chiyoda-Ku Tokoyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010
TAIWAN Linear Technology Corporation Rm. 801, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-521-7575
GERMANY Linear Technology GMBH Untere Hauptstr. 9 D-8057 Eching Germany Phone: 49-89-3195023 Telex: 17-897457 FAX: 49-89-3194821
SINGAPORE Linear Technology PTE. LTD. 101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398
World Headquarters
Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507
01/21/92
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 0192 10K REV 0
(c) LINEAR TECHNOLOGY CORPORATION 1992

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